There is a class of metal-insulator-silicon (MIS) devices in which the gate is formed in a trench that extends downward from the surface of the silicon or other semiconductor material. The gate is typically formed of polycrystalline silicon (polysilicon) and is insulated from the silicon by a layer of oxide that lines the sidewalls and bottom of the trench. The current flow in such devices is primarily vertical and as a result the cells can be more densely packed. All else being equal, this increases the current carrying capability and reduces the on-resistance of the device. Devices that fit into the general category of MIS devices include metal-oxide-silicon field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs) and MOS-gated thyristors.
A cross-sectional view of a typical N-channel trench-gated MOSFET is shown in FIG. 1. In MOSFET 10, N+ region 11 is the source, P region 12 is the body, and N-epi layer 13 is the drain. Current flows vertically through a channel (denoted by the dashed lines). The sidewalls and bottom of the trench are lined with a gate oxide layer 15 and the trench is filled with doped polysilicon which forms the gate 14. The doped polysilicon in the trench is covered with a layer 16 of borophosphosilicate (BPSG) glass, and electrical contact to the source and body regions is made by a metal layer 17. The gate 14 is contacted in the third dimension (outside the plane of the drawing).
Methods of manufacturing trench-gated devices are well known. The top surface of the silicon is masked and a dry/plasma etch is used to cut the trench. A sacrificial oxide layer is thermally grown on the walls of the trench, and removed, to eliminate crystal damage caused by the dry etch. Then a thin gate oxide layer is thermally grown. Finally, doped polysilicon is used to completely fill the trench and form the gate electrode.
One problem that occurs with trench-gated devices derives from the fact that the gate oxide layer at the bottom of the trench is subjected to the drain operating voltage (in the region designated 18 in FIG. 1). This condition (a) limits the drain-voltage rating of the device, (b) presents a long-term gate oxide reliability problem, and (c) greatly increases the gate-to-drain capacitance of the device, limiting its switching speed.